Technical Field
The present invention generally relates to co-fabricating n-type and p-type transistors. More particularly, the present invention relates to enablement of higher ‘k’ gate dielectric cap in RMG FINFET structure as well as method of reducing or eliminating gate stack sidewall defects when co-fabricating n-type and p-type transistors.
Background Information
When co-fabricating n-type and p-type transistors on a same substrate, a gate stack that is suitable, for example, for n-type transistors may first be formed over both an n-type transistor region and a p-type transistor region of the substrate. The process may then be followed by the removal of a portion of the gate stack over the p-type transistors, which may consequently cause defects in the sidewall of the remaining gate stack over the n-type transistors. These defects may, as a result, affect the performance of subsequently formed n-type transistors.